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? 1997 microchip technology inc. preliminary ds21208a-page 1 m 93lc56a/b features single supply with operation down to 2.5v low power cmos technology - 1 ma active current (typical) -1 m a standby current (maximum) 256 x 8 bit organization (93lc56a) 128 x 16 bit organization (93lc56b) self-timed erase and write cycles (including auto-erase) automatic eral before wral power on/off data protection circuitry industry standard 3-wire serial interface device status signal during erase/write cycles sequential read function 1,000,000 e/w cycles guaranteed data retention > 200 years 8-pin pdip/soic and 8-pin tssop packages available for the following temperature ranges: block diagram description the microchip technology inc. 93lc56a/b are 2k-bit, low-voltage serial electrically erasable proms. the device memory is con?ured as x8 (93lc56a) or x16 bits (93lc56b). advanced cmos technology makes these devices ideal for low power nonvolatile memory applications. the 93lc56a/b is available in standard 8-pin dip, surface mount soic, and tssop packages. the 93lc56ax/bx are only offered in a 150-mil soic package. package type - commercial (c): 0 c to +70 c - industrial (i): -40 c to +85 c vcc vss di cs clk do memory array address decoder address counter data register output buffer mode decode clock generator logic 93lc56a/b cs clk di do 1 2 3 4 8 7 6 5 vcc nc nc vss cs clk di do v cc nc nc vss 93lc56a/b nu vcc cs clk nc vss do di 93lc56a/bx 93lc56a/b cs clk di do 1 2 3 4 8 7 6 5 vcc nc nc vss tssop soic soic 1 2 3 4 dip 8 7 6 5 1 2 3 4 8 7 6 5 2k 2.5v microwire serial eeprom microwire is a registered trademark of national semiconductor.
93lc56a/b ds21208a -page 2 preliminary ? 1997 microchip technology inc. 1.0 electrical chara cteristics 1.1 maxim um ratings* v cc ................................................................................... 7.0v all inputs and outputs w .r .t. vss ................ -0.6v to vcc +1.0v stor age temper ature ..................................... -65 c to +150 c ambient temp . with po w er applied ................. -65 c to +125 c solder ing temper ature of leads (10 seconds) ............. +300 c esd protection on all pins ................................................ 4 kv *notice: stresses abo v e those listed under ?axim um r atings ma y cause per manent damage to the de vice . this is a stress r ating only and functional oper ation of the de vice at those or an y other conditions abo v e those indicated in the oper ational listings of this speci cation is not implied. exposure to maxim um r ating conditions f or e xtended per i- ods ma y aff ect de vice reliability . t able 1-1 pin function t ab le name function cs chip select clk ser ial data cloc k di ser ial data input do ser ial data output v ss ground nc no connect v cc p o w er supply t able 1-2 dc and a c electrical characteristics all par ameters apply o v er the speci ed oper ating r anges unless otherwise noted commercial (c): v cc = +2.5v to +6.0v t amb = 0 c to +70 c industr ial (i): v cc = +2.5v to +6.0v t amb = -40 c to +85 c p arameter symbol min. max. units conditions high le v el input v oltage v ih 1 2.0 vcc +1 v 2.7v v cc 5.5v ( note 2 ) v ih 2 0.7 vcc vcc +1 v v cc < 2.7v lo w le v el input v oltage v il 1 -0.3 0.8 v v cc > 2.7v ( note 2 ) v il 2 -0.3 0.2 vcc v v cc < 2.7v lo w le v el output v oltage v ol 1 0.4 v i ol = 2.1 ma; vcc = 4.5v v ol 2 0.2 v i ol =100 m a; vcc = vcc min. high le v el output v oltage v oh 1 2.4 v i oh = -400 m a; vcc = 4.5v v oh 2 vcc-0.2 v i oh = -100 m a; vcc = vcc min. input leakage current i li -10 10 m a v in = v ss output leakage current i lo -10 10 m a v out = v ss pin capacitance (all inputs/outputs) c in , c out 7 pf v in /v out = 0 v (notes 1 & 2) t amb = +25 c , fclk = 1 mhz oper ating current i cc read 1 500 ma m a f clk = 2 mhz; v cc = 6.0v f clk = 1 mhz; v cc = 3.0v i cc wr ite 1.5 ma standb y current i ccs 1 m a cs = v ss cloc k frequency f clk 2 1 mhz mhz v cc > 4.5v v cc < 4.5v cloc k high time t ckh 250 ns cloc k lo w time t ckl 250 ns chip select setup time t css 50 ns relativ e to clk chip select hold time t csh 0 ns relativ e to clk chip select lo w time t csl 250 ns data input setup time t dis 100 ns relativ e to clk data input hold time t dih 100 ns relativ e to clk data output dela y time t pd 400 ns cl = 100 pf data output disab le time t cz 100 ns cl = 100 pf (note 2) status v alid time t sv 500 ns cl = 100 pf prog r am cycle time t wc 6 ms erase/write mode t ec 6 ms eral mode t wl 15 ms wral mode endur ance 1m cycles 25 c , v cc = 5.0v , bloc k mode ( note 3 ) note 1: this par ameter is tested at t amb = 25 c and f clk = 1 mhz. 2: this par ameter is per iodically sampled and not 100% tested. 3: this application is not tested b ut guar anteed b y char acter ization. f or endur ance estimates in a speci c application, please consult the t otal endur ance model which ma y be obtained on microchip s bbs or w ebsite .
93lc56a/b ? 1997 microchip technology inc. preliminary ds21208a -page 3 2.0 pin description 2.1 chip select (cs) a high le v el selects the de vice; a lo w le v el deselects the de vice and f orces it into standb y mode . ho w e v er , a pro- g r amming cycle which is already in prog ress will be completed, regardless of the chip select (cs) input signal. if cs is brought lo w dur ing a prog r am cycle , the de vice will go into standb y mode as soon as the pro- g r amming cycle is completed. cs m ust be lo w f or 250 ns minim um ( t csl ) betw een consecutiv e instr uctions . if cs is lo w , the inter nal con- trol logic is held in a reset status . 2.2 serial cloc k (clk) the ser ial cloc k is used to synchroniz e the comm uni- cation betw een a master de vice and the 93lc56a/b . opcode , address , and data bits are cloc k ed in on the positiv e edge of clk. data bits are also cloc k ed out on the positiv e edge of clk. clk can be stopped an ywhere in the tr ansmission sequence (at high or lo w le v el) and can be contin ued an ytime with respect to cloc k high time ( t ckh ) and cloc k lo w time ( t ckl ). this giv es the controlling master freedom in prepar ing opcode , address , and data. clk is a ?on't care if cs is lo w (de vice deselected). if cs is high, b ut st ar t condition has not been detected, an y n umber of cloc k cycles can be receiv ed b y the de vice without changing its status (i.e ., w aiting f or st ar t condition). clk cycles are not required dur ing the self-timed write (i.e ., auto erase/write) cycle . after detection of a st ar t condition the speci ed n um- ber of cloc k cycles (respectiv ely lo w to high tr ansitions of clk) m ust be pro vided. these cloc k cycles are required to cloc k in all required opcode , address , and data bits bef ore an instr uction is e x ecuted ( t ab le 2-1 and t ab le 2-2 ). clk and di then become don't care inputs w aiting f or a ne w st ar t condition to be detected. 2.3 data in (di) data in is used to cloc k in a st ar t bit, opcode , address , and data synchronously with the clk input. 2.4 data out (do) data out is used in the read mode to output data syn- chronously with the clk input ( t pd after the positiv e edge of clk). this pin also pro vides read y/ b usy status inf or mation dur ing erase and write cycles . read y/ b usy sta- tus inf or mation is a v ailab le on the do pin if cs is brought high after being lo w f or minim um chip select lo w time ( t csl ) and an erase or write oper ation has been initiated. the status signal is not a v ailab le on do , if cs is held lo w dur ing the entire erase or write cycle . in this case , do is in the high-z mode . if status is chec k ed after the erase/write cycle , the data line will be high to indicate the de vice is ready . t able 2-1 instruction set f or 93lc56a instruction sb opcode ad dress data in data out req. clk cyc les erase 1 11 x a7 a6 a5 a4 a3 a2 a1 a0 (rd y/ bsy ) 12 eral 1 00 1 0 x x x x x x x (rd y/ bsy ) 12 ewds 1 00 0 0 x x x x x x x high- z 12 ewen 1 00 1 1 x x x x x x x high- z 12 read 1 10 x a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 20 write 1 01 x a7 a6 a5 a4 a3 a2 a1 a0 d7 - d0 (rd y/ bsy ) 20 wral 1 00 0 1 x x x x x x x d7 - d0 (rd y/ bsy ) 20 t able 2-2 instruction set f or 93lc56b instruction sb opcode ad dress data in data out req. clk cyc les erase 1 11 x a6 a5 a4 a3 a2 a1 a0 (rd y/ bsy ) 11 eral 1 00 1 0 x x x x x x (rd y/ bsy ) 11 ewds 1 00 0 0 x x x x x x high- z 11 ewen 1 00 1 1 x x x x x x high- z 11 read 1 10 x a6 a5 a4 a3 a2 a1 a0 d15 - d0 27 write 1 01 x a6 a5 a4 a3 a2 a1 a0 d15 - d0 (rd y/ bsy ) 27 wral 1 00 0 1 x x x x x x d15 - d0 (rd y/ bsy ) 27
93lc56a/b ds21208a -page 4 preliminary ? 1997 microchip technology inc. 3.0 functional description instr uctions , addresses and wr ite data are cloc k ed into the di pin on the r ising edge of the cloc k (clk). the do pin is nor mally held in a high-z state e xcept when reading data from the de vice , or when chec king the read y/ b usy status dur ing a prog r amming oper ation. the read y/ b usy status can be v er i ed dur ing an erase/write oper ation b y polling the do pin; do lo w indicates that prog r amming is still in prog ress , while do high indicates the de vice is ready . the do will enter the high- z state on the f alling edge of the cs . 3.1 st ar t condition the st ar t bit is detected b y the de vice if cs and di are both high with respect to the positiv e edge of clk f or the rst time . bef ore a st ar t condition is detected, cs , clk, and di ma y change in an y combination (e xcept to that of a st ar t condition), without resulting in an y de vice oper- ation (erase, eral, ewds , ewen, read , write, and wral). as soon as cs is high, the de vice is no longer in the standb y mode . an instr uction f ollo wing a st ar t condition will only be e x ecuted if the required amount of opcode , address and data bits f or an y par ticular instr uction is cloc k ed in. after e x ecution of an instr uction (i.e ., cloc k in or out of the last required address or data bit) clk and di become don't care bits until a ne w st ar t condition is detected. 3.2 d a t a in (di) and d a t a out (do) it is possib le to connect the data in (di) and data out (do) pins together . ho w e v er , with this con gur ation, if a0 is a logic-high le v el, it is possib le f or a ? us con ict to occur dur ing the ?umm y z ero that precedes the read oper ation. under such a condition, the v oltage le v el seen at do is unde ned and will depend upon the relativ e impedances of do and the signal source dr iv- ing a0. the higher the current sourcing capability of a0, the higher the v oltage at the do pin. 3.3 data pr otection dur ing po w er-up , all prog r amming modes of oper ation are inhibited until vcc has reached a le v el g reater than 2.2v . dur ing po w er-do wn, the source data protection circuitr y acts to inhibit all prog r amming modes when vcc has f allen belo w 2.2v at nominal conditions . the ewds and ewen commands giv e additional pro- tection against accidentally prog r amming dur ing nor mal oper ation. after po w er-up , the de vice is automatically in the ewds mode . theref ore , an ewen instr uction m ust be perf or med bef ore an y erase or write instr uction can be e x ecuted. figure 3-1: synchr onous d a t a timing cs v ih v il v ih v il v ih v il v oh v ol v oh v ol clk di do (read) do (program) t css t dis t ckh t ckl t dih t pd t csh t pd t cz status valid t sv t cz note: a c t est conditions: v il = 0.4v , v ih - 2.4v .
93lc56a/b ? 1997 microchip technology inc. preliminary ds21208a -page 5 3.4 erase the erase instr uction f orces all data bits of the spec- i ed address to the logical ? state . cs is brought lo w f ollo wing the loading of the last address bit. this f alling edge of the cs pin initiates the self-timed prog r amming cycle . the do pin indicates the read y/ b usy status of the de vice if cs is brought high after a minim um of 250 ns lo w ( t csl ). do at logical ? indicates that prog r am- ming is still in prog ress . do at logical ? indicates that the register at the speci ed address has been er ased and the de vice is ready f or another instr uction. 3.5 erase all (eral) the eral instr uction will er ase the entire memor y arr a y to the logical ? state . the eral cycle is identical to the erase cycle e xcept f or the diff erent opcode . the eral cycle is completely self-timed and commences at the f alling edge of the cs . cloc king of the clk pin is not necessar y after the de vice has entered the eral cycle . the do pin indicates the read y/ b usy status of the de vice if cs is brought high after a minim um of 250 ns lo w ( t csl ) and bef ore the entire eral cycle is com- plete . figure 3-2: erase timing figure 3-3: eral timing cs clk di do t csl check status 1 1 1 a n a n -1 a n -2 a0 t sv t cz busy ready high-z t wc high-z cs clk di do t csl check status 1 0 0 1 0 x x t sv t cz busy ready high-z t ec high-z guar anteed at vcc = 4.5v to +6.0v .
93lc56a/b ds21208a -page 6 preliminary ? 1997 microchip technology inc. 3.6 erase/write disab le and enab le (ewds/ewen) the 93lc56a/b po w ers up in the erase/write disab le (ewds) state . all prog r amming modes m ust be preceded b y an erase/write enab le (ewen) instr uction. once the ewen instr uction is e x ecuted, prog r amming remains enab led until an ewds instr uc- tion is e x ecuted or v cc is remo v ed from the de vice . t o protect against accidental data disturbance , the ewds instr uction can be used to disab le all erase/write functions and should f ollo w all prog r amming oper a- tions . ex ecution of a read instr uction is independent of both the ewds and ewen instr uctions . 3.7 read the read instr uction outputs the ser ial data of the addressed memor y location on the do pin. a dumm y z ero bit precedes the 8-bit ( 93lc56a ) or 16-bit ( 93lc56b ) output str ing. the output data bits will toggle on the r ising edge of the clk and are stab le after the speci ed time dela y (t pd ). sequential read is possib le when cs is held high. the memor y data will automati- cally cycle to the ne xt register and output sequentially . figure 3-4: ewds timing figure 3-5: ewen timing figure 3-6: read timing cs clk di 1 0 0 0 0 x x t csl 1 x cs clk di 0 0 1 1 x t csl cs clk di do 1 1 0 an a0 high-z 0 dx d0 dx d0 dx d0
93lc56a/b ? 1997 microchip technology inc. preliminary ds21208a -page 7 3.8 write the write instr uction is f ollo w ed b y 8 bits (93lc56a) or 16 bits (93lc56b) of data which are wr itten into the speci ed address . after the last data bit is put on the di pin, the f alling edge of cs initiates the self-timed auto- er ase and prog r amming cycle . the do pin indicates the read y/ b usy status of the de vice if cs is brought high after a minim um of 250 ns lo w ( t csl ) and bef ore the entire wr ite cycle is complete . do at logical ? indicates that prog r amming is still in prog ress . do at logical ? indicates that the register at the speci ed address has been wr itten with the data speci ed and the de vice is ready f or another instr uc- tion. 3.9 write all (wral) the wr ite all (wral) instr uction will wr ite the entire memor y arr a y with the data speci ed in the command. the wral cycle is completely self-timed and com- mences at the f alling edge of the cs . cloc king of the clk pin is not necessar y after the de vice has entered the wral cycle . the wral command does include an automatic eral cycle f or the de vice . theref ore , the wral instr uction does not require an eral instr uction b ut the chip m ust be in the ewen status . the do pin indicates the read y/ b usy status of the de vice if cs is brought high after a minim um of 250 ns lo w ( t csl ). figure 3-7: write timing figure 3-8: wral timing cs clk di do 1 0 1 an a0 dx d0 b usy read y high-z high-z t wc t csl t cz t sv cs clk di do high-z 1 0 0 0 1 x x dx d0 high-z b usy read y t wl guar anteed at vcc = 4.5v to +6.0v . t csl t sv t cz
93lc56a/b ds21208a -page 8 preliminary ? 1997 microchip technology inc. notes:
93lc56a/b ? 1997 microchip technology inc. preliminary ds21208a -page 9 notes:
93lc56a/b ds21208a -page 10 preliminary ? 1997 microchip technology inc. notes:
93lc56a/b ? 1997 microchip technology inc. preliminary ds21208a -page 11 93lc56a/b pr oduct identification system t o order or obtain inf or mation, e .g., on pr icing or deliv er y , ref er to the f actor y or the listed sales of ce . sales and suppor t p ac ka g e: p = plastic dip (300 mil body), 8-lead sn = plastic soic (150 mil body), 8-lead sm = plastic soic (208 mil body), 8-lead st = tssop , 8-lead t emperature blank = 0 c to +70 c rang e: i = -40 c to +85 c de vice: 93lc56a 2k micro wire ser ial eepr om (x8) 93lc56a t 2k micro wire ser ial eepr om (x8) t ape and reel 93lc56a x 2k micro wire ser ial eepr om (x8) in alter nate pinout (sn only) 93lc56a xt 2k micro wire ser ial eepr om (x8) in alter nate pinout, t ape and reel (sn only) 93lc56b 2k micro wire ser ial eepr om (x16) 93lc56b t 2k micro wire ser ial eepr om (x16) t ape and reel 93lc56b x 2k micro wire ser ial eepr om (x16) in alter nate pinout (sn only) 93lc56b xt 2k micro wire ser ial eepr om (x16) in alter nate pinout, t ape and reel (sn only) 93lc56a/b /p data sheets products suppor ted b y a preliminar y data sheet ma y ha v e an err ata sheet descr ibing minor oper ational diff erences and recom- mended w or karounds . t o deter mine if an err ata sheet e xists f or a par ticular de vice , please contact one of the f ollo wing: 1. y our local microchip sales of ce . 2. the microchip cor por ate liter ature center u .s . f ax: (602) 786-7277. 3. the microchip s bulletin board, via y our local compuser v e n umber (compuser v e membership no t required).
in f o r mation contained in this publication regarding d e vice applications and the like is intended f or suggestion only and may be superseded by updates . no representation or w arranty is gi v en and no liability is assumed by microchi p t echnology inco r porated with respect to the accu r acy or use of such in f o r mation, or inf r ingement of patents or other intellectual prope r ty r ights a r ising from such use or otherwis e . use of microchip s products as c r itical components in li f e suppo r t systems is not autho r i z ed e xcept with e xpress w r itten appro v al b y microchi p . no licenses are con v e y ed, implicitly or otherwise, under any intellectual prope r ty r ight s . the microchip logo and name are registered t r adema r ks of microchi p t echnology inc . in the u . s .a . and other count r ie s . all r ights rese r v ed . all other tradema r ks mentioned herein are the prope r ty of their respective companies. ds 2120 8 a-page 12 preliminary ? 1997 microchip technology inc. w orldwide s ales & s ervice americas corporate of?e microchip t echnolog y inc. 235 5 w est chandler blvd. chandle r , az 85224-6199 t el : 602-786-7200 f ax : 602-786-7277 technical support: 602 786-7627 web: http://ww w .microchi p .com atlanta microchip t echnolog y inc. 500 sugar mill road, suite 200b atlanta, ga 30350 t el : 770-640-0034 f ax : 770-640-0307 boston microchip t echnolog y inc. 5 mount r o y al a v enue ma r lborough, ma 01752 t el : 508-480-9990 f ax : 508-480-8575 chicago microchip t echnolog y inc. 333 pierce road, suite 180 itasca, il 60143 t el : 630-285-0071 f ax : 630-285-0075 dallas microchip t echnolog y inc. 14651 dallas p a r k w a y , suite 816 dalla s , tx 75240-8809 t el : 972-991-7177 f ax : 972-991-8588 d a yton microchip t echnolog y inc. t wo prestige plac e , suite 150 miamis b urg, oh 45342 t el : 937-291-1654 f ax : 937-291-9175 los angeles microchip t echnolog y inc. 1820 1 v on ka r man, suite 1090 i r vin e , ca 92612 t el : 714-263-1888 f ax : 714-263-1338 n e w y ork microchip t echnolog y inc. 150 motor p a r k w a y , suite 416 hauppaug e , ny 11788 t el : 516-273-5305 f ax : 516-273-5335 san jose microchip t echnolog y inc. 2107 no r th first street, suite 590 san jos e , ca 95131 t el : 408-436-7950 f ax : 408-436-7955 t o r onto microchip t echnolog y inc. 5925 ai r po r t road, suite 200 mississauga, onta r io l4v 1w1, canada t el : 905-405-6279 f ax : 905-405-6253 asia/ p a cific hong k ong microchip asia p aci? r m 3801 b , t o wer t wo metroplaza 223 hing f ong road k w ai f ong, n. t ., hong k ong t el : 852-2-401-1200 f ax : 852-2-401-3431 india microchip t echnolog y india n o . 6, legac y , co n v ent road bangalore 560 025, india t el : 91-80-229-0061 f ax : 91-80-229-0062 k orea microchip t echnolog y k orea 168-1 , y oungbo bldg . 3 floor samsung-dong, kangnam- k u seoul, k orea t el : 82-2-554-7200 f ax : 82-2-558-5934 shanghai microchip t echnology rm 406 shanghai golden b r idge bldg. 207 7 y an?n roa d w est, hongiao dist r ict shanghai, prc 200335 t el : 86-21-6275-5700 f ax : 86 21-6275-5060 singapore microchip t echnology t ai w an singapore branch 200 middle road #10-03 p r ime centre singapore 188980 t el : 65-334-8870 f ax : 65-334-8850 t aiwan , r. o .c microchip t echnology t ai w an 10f-1c 207 t ung hua no r th road t aipei, t ai w an , r o c t el : 886 2-717-7175 f ax : 886-2-545-0139 eu r ope united kingdom a r i z ona microchi p t echnology ltd. unit 6 , the cou r t y ard mead o w bank, fu r long road bou r ne end, bu c kinghamshire sl8 5aj t el : 44-1628-851077 f ax : 44-1628-850259 france a r i z ona microchi p t echnology sarl zone indust r ielle de la bonde 2 rue du buisson aux f raises 91300 mass y , f rance t el : 33-1-69-53-63-20 f ax : 33-1-69-30-90-79 germa n y a r i z ona microchi p t echnology gmbh gust a v-heinemann-ring 125 d-81739 m?chen, ge r ma n y t el : 49-89-627-144 0 f ax : 49-89-627-144-44 ita l y a r i z ona microchi p t echnology srl centro direzionale colleone p alaz z o t au r us 1 v . le colleoni 1 20041 agrate b r ianza milan, italy t el : 39-39-6899939 f ax : 39-39-6899883 j a p a n microchi p t echnology intl . inc. ben e x s-1 6f 3-18-20, shi n y o k ohama k ohoku- k u, y o k ohama kanag a w a 222 j apan t el : 81-4-5471- 6166 f ax : 81-4-5471-6122 5/8/97 p r inted on recycled pape r . all r ights rese r v ed . ?1997, microchi p t echnology inco r porated, usa . 6/97 m

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